6692 – Core3S500E/en

Documentation notice: This technical documentation was independently rewritten from an archived supplier source. Check technical details and commands against the product version and manufacturer documentation before use.

Summary

Technical overview of the Waveshare Core3S500E core board based on the Xilinx XC3S500E FPGA. Covers hardware basics, power supply voltages, JTAG programming, and quick-start examples.

Related products at JW Tech

• 6692 – Core3S500E, XILINX Core Board
• WSAL6692 – Core3S500E, XILINX Core Board

Technical overview

• The core board is built around the Xilinx XC3S500E SRAM-based FPGA; configuration data resides in SRAM and must be reloaded at every power-up.
• Power supply: A 5 V input is converted via AMS1117 regulators to 3.2 V (VCC3.3), 2.5 V (VCC2.5), and 1.2 V (VCC1.2); a PWR_LED on 3.3 V indicates power status.
• Clock circuit: An onboard 50 MHz crystal oscillator provides the timing signal through a dedicated global clock input (GCLK/CLK).
• Reset circuit: An RC reset with a RESET button generates an active-low reset; pressing nCONFIG triggers FPGA reconfiguration without a full reboot.
• JTAG interface: TDI, TDO, TMS, TCK pins are present; programming uses a Platform Cable USB programmer plus a JTAG adapter; files for the XCF04S PROM must be converted to .msc format.
• Configuration PROM: An XCF04SA (4 Mbit) retains configuration data without power and supports in-system programming via JTAG.
• LED circuit: Four onboard LEDs are each driven by dedicated FPGA pins; a low level on the LED pin turns the corresponding LED on.
• Extension boards: Waveshare Open boards follow a core-extension separation concept; interfaces are designed for compatibility with other FPGA boards.

Notes and version constraints

• Verify the exact pin mapping and correct orientation of the JTAG adapter (arrow pointing up) before programming.
• The source mentions a known issue where power is lost when flashing; the solution only points to an external link that is not available here – please contact the manufacturer for details.
• Several tests require additional extension boards (joystick, push buttons, SEG LED, keypad, sensors, etc.); without these boards the examples will not work.
• IO voltage levels (VCCO_0/1/2/3) can be set to 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V depending on the design; confirm the appropriate setting for your application.

Source and revision record

• Core3S500E - Waveshare Wiki
• Source revision: 104252
• Captured: 2026-08-29T09:02:29+00:00
• SHA-256: 41cfccba1388ffc564b637f9de651f68e6e6a0cbcac502ef9b3543266408cee7