6704 – Open3S500E/en

Documentation notice: This technical documentation was independently rewritten from an archived supplier source. Check technical details and commands against the product version and manufacturer documentation before use.

Summary

The Open3S500E is an FPGA development board featuring the XILINX XC3S500E. It provides 5V operation, JTAG programming via a Platform Cable USB, and various I/O interfaces for expansion boards.

Related products at JW Tech

• 6704 – Open3S500E Standard, XILINX Development Board
• 6705 – Open3S500E Package A, XILINX Development Board
• 6706 – Open3S500E Package B, XILINX Development Board
• WSAL6704 – Open3S500E Standard, XILINX Development Board
• WSAL6705 – Open3S500E Package A, XILINX Development Board
• WSAL6706 – Open3S500E Package B, XILINX Development Board

Technical overview

• Onboard: XILINX XC3S500E (Spartan-3E), voltage regulators AMS1117, configuration PROM XCF04S (4 Mbit), 50 MHz crystal oscillator, JTAG interface, four LEDs and reset buttons.
• Power supply: 5 V input is regulated to 3.3 V, 2.5 V and 1.2 V; VCCINT and VCCAUX each require 2.5 V; VCCO banks can be supplied at 3.3/2.5/1.8/1.5/1.2 V.
• Clock circuit: A 50 MHz crystal drives the global clock input CLK; this clock controls the FPGA registers.
• Reset circuit: RC reset via RESET button (active-low); pressing the nCONFIG key triggers reconfiguration without a reboot.
• Configuration: Loads bitstreams into the SRAM-based logic; data are stored in the XCF04S PROM and persist without power.
• JTAG interface: Standard pins TDI, TDO, TMS, TCK; programming uses a dedicated programmer (Platform Cable USB) plus a JTAG adapter; the arrow on the adapter must point upward.
• LEDs: Four onboard LEDs are driven by individual FPGA pins; a low signal on the LED pin turns the corresponding LED on.
• Expansion interfaces: The series follows the core-expansion concept; core and expansion boards are designed to remain compatible with other FPGA boards.
• Example tests: 17 demos covered, including LED blink, joystick, 8 push buttons, 8-segment LED board, 4x4 keypad, DS18B20, buzzer, PS/2 keyboard, VGA, LCD1602, LCD12864, USB communication, UART, I2C EEPROM, AT45DB, PCF8563 RTC, PCF8591 A/D.
• Verilog and VHDL examples are available for most tests; some tests are provided only in Verilog (DS18B20, AT45DBXX_SPI, PCF8563, PCF8591).

Notes and version constraints

• No explicit commands or command sequences were provided in the source; therefore the commands field remains empty.
• The JTAG adapter must be correctly oriented (arrow pointing up), otherwise programming may fail.
• Bitstreams are reloaded on every reboot because the logic is SRAM-based; without power, the configuration is lost.
• For demo tests, the respective expansion boards must be connected to the correct interfaces (e.g., 8I/Os_2, 16I/Os_2, LCD1602, etc.).
• Some tests require additional modules (joystick, 8-button board, 8-segment LED board, 4x4 keypad, DS18B20, buzzer, PS/2 keyboard, VGA, LCDs, USB module, I2C EEPROM, AT45DB, PCF8563, PCF8591).
• The exact firmware/software version and precise pin mappings are not fully specified in the source; the current documentation should be checked before starting.

Source and revision record

• Open3S500E - Waveshare Wiki
• Source revision: 104253
• Captured: 2026-08-29T09:03:41+00:00
• SHA-256: de77e662c9020e0436c6c2e997cdd1e6bb02815fb2fa163a742cd949300ab83e