https://wiki.jw-tech.eu/index.php?action=history&feed=atom&title=6692_%E2%80%93_Core3S500E%2Fen 2026-10-23T21:46:25Z Versionsgeschichte dieser Seite in JW Tech Wiki MediaWiki 1.43.9 https://wiki.jw-tech.eu/index.php?title=6692_%E2%80%93_Core3S500E/en&diff=1710&oldid=prev 2026-09-05T22:35:17Z

<p>Freigegebene technische Dokumentation veröffentlicht; Text-only und noindex</p> <p><b>Neue Seite</b></p><div>__NOINDEX__<br /> &#039;&#039;&#039;Documentation notice:&#039;&#039;&#039; This technical documentation was independently rewritten from an archived supplier source. Check technical details and commands against the product version and manufacturer documentation before use.<br /> <br /> == Summary ==<br /> Technical overview of the Waveshare Core3S500E core board based on the Xilinx XC3S500E FPGA. Covers hardware basics, power supply voltages, JTAG programming, and quick-start examples.<br /> <br /> == Related products at JW Tech ==<br /> * [https://shop.jw-tech.eu/p/6692 6692 – Core3S500E, XILINX Core Board]<br /> * [https://shop.jw-tech.eu/p/WSAL6692 WSAL6692 – Core3S500E, XILINX Core Board]<br /> <br /> == Technical overview ==<br /> * The core board is built around the Xilinx XC3S500E SRAM-based FPGA; configuration data resides in SRAM and must be reloaded at every power-up.<br /> * Power supply: A 5 V input is converted via AMS1117 regulators to 3.2 V (VCC3.3), 2.5 V (VCC2.5), and 1.2 V (VCC1.2); a PWR_LED on 3.3 V indicates power status.<br /> * Clock circuit: An onboard 50 MHz crystal oscillator provides the timing signal through a dedicated global clock input (GCLK/CLK).<br /> * Reset circuit: An RC reset with a RESET button generates an active-low reset; pressing nCONFIG triggers FPGA reconfiguration without a full reboot.<br /> * JTAG interface: TDI, TDO, TMS, TCK pins are present; programming uses a Platform Cable USB programmer plus a JTAG adapter; files for the XCF04S PROM must be converted to .msc format.<br /> * Configuration PROM: An XCF04SA (4 Mbit) retains configuration data without power and supports in-system programming via JTAG.<br /> * LED circuit: Four onboard LEDs are each driven by dedicated FPGA pins; a low level on the LED pin turns the corresponding LED on.<br /> * Extension boards: Waveshare Open boards follow a core-extension separation concept; interfaces are designed for compatibility with other FPGA boards.<br /> <br /> == Notes and version constraints ==<br /> * Verify the exact pin mapping and correct orientation of the JTAG adapter (arrow pointing up) before programming.<br /> * The source mentions a known issue where power is lost when flashing; the solution only points to an external link that is not available here – please contact the manufacturer for details.<br /> * Several tests require additional extension boards (joystick, push buttons, SEG LED, keypad, sensors, etc.); without these boards the examples will not work.<br /> * IO voltage levels (VCCO_0/1/2/3) can be set to 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V depending on the design; confirm the appropriate setting for your application.<br /> <br /> == Source and revision record ==<br /> * [https://www.waveshare.com/wiki/Core3S500E Core3S500E - Waveshare Wiki]<br /> * Source revision: 104252<br /> * Captured: 2026-08-29T09:02:29+00:00<br /> * SHA-256: &lt;code&gt;41cfccba1388ffc564b637f9de651f68e6e6a0cbcac502ef9b3543266408cee7&lt;/code&gt;</div>

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